1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device capable of efficiently detecting a defect during a burn-in test.
2. Description of the Background Art
Generally, device failures are caused roughly in the three periods of the initial failure period, the accidental failure period and the ware-out failure period in order of time.
In the initial failure period, defects which are caused during the device manufacturing process come to the surface as failures, and initial failures appear immediately after the start of use. The initial failure rate decreases rapidly with time.
Thereafter, the accidental failure period follows during which a low failure rate continues for a certain period.
Then, the device comes closer to its useful life and enters the ware-out failure period during which the failure rate increases rapidly.
Desirably, the device is used within the accidental failure period. This period corresponds to the useful life. In order to improve the device reliability, therefore, it is necessary that the accidental failure period with a low and constant failure rate continues long.
Meanwhile, in order to eliminate initial failures in advance, it is necessary to perform a screening process. In the screening process, an acceleration operation for aging is applied for a prescribed period so that any defect is made conspicuous, and a defective device found as a result is rejected. For a short term and effective screening process, such a screening test that reveals an initial failure in a short time is desirably performed.
Currently, a high temperature operation test (burn-in test) is generally conducted as one of the screening methods. The burn-in test can directly evaluate a dielectric film of an actual device, and the test reveals every defect cause including migration of an aluminum interconnection by applying high temperature and high electric field stresses. In recent years, the burn-in test as described above has been performed against a wafer before a semiconductor memory device is packaged, and a large number of chips have been tested at a time.
FIG. 7 is a circuit diagram showing a circuit configuration concerning a burn-in test in a conventional semiconductor memory device.
Referring to FIG. 7, a row decoder of the conventional semiconductor memory device includes a predecode circuit 26a, a main decode circuit 326b for driving even-numbered word lines WL0, WL2 according to an output of predecode circuit 26a, row address signals RA0, RA1, a potential at a pad PD0 for testing (hereinafter, referred to as test pad PD0) and a test signal TMRS, and a main decode circuit 326c for driving odd-numbered word lines WL1, WL3 according to the output of predecode circuit 26a, row addresses RA0, RA1, a potential at a pad PD1 for testing (hereinafter, referred to as test pad RA1) and test signal TMRS.
Predecode circuit 26a includes an AND circuit 52 for receiving row address signals /RA2, /RA3 and outputting a signal X4, an AND circuit 54 for receiving row address signals /RA4, /RA5 and outputting a signal X8, and an AND circuit 56 for receiving row address signals /RAG, /RA7 and outputting a signal X12.
Main decode circuit 326b includes a composite gate circuit 362 for driving a signal RX0 to the high level (hereinafter, referred to as the H level) when test signal TMRS is at the low level (hereinafter, referred to as the L level) and row address signals /RA0, /RA1 are both at the H level and for driving signal RX0 to the H level according to the potential at test pad PD0 when test signal TMRS is at the H level.
Main decode circuit 326b further includes a composite gate circuit 364 for driving a signal RX2 to the H level when test signal TMRS is at the L level and row address signals /RA0, /RA1 are both at the H level and for driving signal RX2 to the H level according to the potential at test pad PD0 when test signal TMRS is at the H level.
Main decode circuit 326b further includes a composite gate circuit 368 for driving its output to the H level when test signal TMRS is at the L level and signals X4, X8, X12 are all at the H level.
Main decode circuit 326b further includes a word driver 70 for activating word line WL0 when signal RX0 and the output of composite gate circuit 368 are at the H and L levels, respectively, and a word driver 72 for activating word line WL2 when signal RX2 and the output of composite circuit 368 are at the H and L levels, respectively.
Word driver 70 includes a P channel MOS transistor 74 and an N channel MOS transistor 76 which are connected in series between a node supplied with signal RX0 and a ground node. The gates of N channel MOS transistor 76 and P channel MOS transistor 74 are supplied with the output of composite gate circuit 368. A node for connecting P channel MOS transistor 74 and N channel MOS transistor 76 is connected to word line WL0.
Word driver 72 includes a P channel MOS transistor 78 and an N channel MOS transistor 80 which are connected in series between a node supplied with signal RX2 and the ground node. The gates of P channel MOS transistor 78 and N channel MOS transistor 80 are supplied with the output of composite gate circuit 308. A node for connecting P channel MOS transistor 78 and N channel MOS transistor 80 is connected to word line WL2.
Main decode circuit 326c includes a composite gate circuit 382 for driving a signal RX1 to the H level when test signal TMRS is at the L level and row address signals RA0, /RA1 are both at the H level and for driving signal RX1 to the H level according to the potential at test pad PD1 when test signal TMRS is at the H level.
Main decode circuit 326c further includes a composite gate circuit 384 for driving a signal RX3 to the H level when test signal TMRS is at the L level and row address signals RA0, RA1 are both at the H level and for driving signal RX3 to the H level according to the potential at test pad RA1 when test signal TMRS is at the H level.
Main decode circuit 326c further includes a composite gate circuit 388 for driving its output to the H level when test signal TMRS is at the L level and signals X4, X8, X12 are all at the H level.
Main decode circuit 326c further includes a word driver 90 for activating word line WL1 when signal RX1 and the output of composite gate circuit 388 are at the H and L levels, respectively, and a word driver 92 for activating word line WL3 when signal RX3 and the output of composite gate circuit 388 are at the H and L levels, respectively.
Word driver 90 includes a P channel MOS transistor 94 and an N channel MOS transistor 96 which are connected in series between a node supplied with signal RX1 and the ground node. The gates of N channel MOS transistor 96 and P channel MOS transistor 94 are supplied with the output of composite gate circuit 388. A node for connecting P channel MOS transistor 74 and N channel MOS transistor 76 is connected to word line WL1.
Word driver 92 includes a P channel MOS transistor 98 and an N channel MOS transistor 100 which are connected in series between a node supplied with signal RX3 and the ground node. The gates of P channel MOS transistor 98 and N channel MOS transistor 100 are supplied with the output of composite gate circuit 388. A node for connecting P channel MOS transistor 98 and N channel MOS transistor 100 is connected to word line WL3.
In short, the conventional semiconductor memory device has a circuit configuration in which the word lines are divided into two groups of even-numbered and odd-numbered sides and the potential of each word line group can be controlled from two dedicated pads in order to detect a burn-in defect.
In the conventional semiconductor memory device, the circuit shown in FIG. 7 is used to collectively activate or inactivate the even-numbered word line group and the odd-numbered word line group so as to provide a potential difference between the even-numbered word line group and the odd-numbered word line group. Thus, stress is applied to the semiconductor memory device to eliminate a burn-in defect.
However, in the conventional circuit configuration as described above, the word lines included in the even-numbered word line group always have an identical potential. Similarly, the word lines included in the odd-numbered word line group always have an identical potential. For such potential application, if the even-numbered word lines are arranged close to each other or the odd-numbered word lines are arranged close to each other, stress cannot be applied to a defect portion such as a leakage defect if it is found where the word lines are closely arranged, and the defect cannot be eliminated by using the burn-in test.
FIG. 8 is a schematic view for illustrating a defect which cannot be eliminated by the conventional circuit configuration.
Referring to FIG. 8, when word lines WL0, WL1, and WL2 are arranged in parallel in this order, word lines WL0, WL2 are provided with contact windows C0, C2 and word line WL1 includes a portion, which is not provided with a contact window, near contact windows C0, C2. If such a portion is etched excessively in a process for providing the contact windows, a conductive material filled in the contact windows may cause a leakage defect.
FIG. 9 is a circuit diagram for illustrating the defect portion shown in FIG. 8.
Referring to FIG. 9, the conventional semiconductor memory device includes word drivers 392, 396, 394 and 398 for activating word lines WL0 to WL3, respectively.
Here, word drivers 392, 394 provided for even-numbered word lines WL0, WL2 are arranged on the same side of a memory array, and word drivers 396, 398 for driving odd-numbered word lines WL1, WL3 are arranged on the opposite side of the memory array with respect to word drivers 392, 394 for driving the even-numbered word lines.
Word driver 392 includes a P channel MOS transistor 402 and an N channel MOS transistor 404 which are connected in series between a node supplied with a predecode signal RX0 and a ground node. The gates of P channel MOS transistor 402 and N channel MOS transistor 404 are supplied with a decoded row address signal IA0.
Word driver 394 includes a P channel MOS transistor 406 and an N channel MOS transistor 408 which are connected in series between a node supplied with a predecode signal RX2 and the ground node. The gates of P channel MOS transistor 406 and N channel MOS transistor 408 are supplied with a decoded row address signal IA1.
Word driver 396 includes a P channel MOS transistor 410 and an N channel MOS transistor 412 which are connected in series between a node supplied with a predecode signal RX1 and the ground node. The gates of P channel MOS transistor 410 and N channel MOS transistor 412 are supplied with a decoded row address signal IA2.
Word driver 398 includes a P channel MOS transistor 414 and an N channel MOS transistor 41G which are connected in series between a node supplied with a predecode signal RX3 and the ground node. The gates of P channel MOS transistor 414 and N channel MOS transistor 416 are supplied with a decoded row address signal IA3.
A node for connecting P channel MOS transistor 402 and N channel MOS transistor 404 is connected to word line WL0 through contact window C0. A node for connecting P channel MOS transistor 406 and N channel MOS transistor 408 is connected to word line WL2 through contact window C2.
Contact windows C0, C2 have the positional relationship as shown in FIG. 9, and any contact window which is to be connected to word line WL1 is not provided near these contact windows. Therefore, if excessive etching is performed to provide contact windows C0, C2 in the conventional semiconductor memory device, the conductive material filled in the contact windows may cause a bridge.
An object of the present invention is to provide a semiconductor memory device with an improved defect elimination rate by a burn-in test, capable of increasing the degree of freedom in setting the potential of each word line and bit line and applying various stresses to portions between the word lines during the burn-in test.
In summary, the present invention is a semiconductor memory device including a memory array, first to fourth word lines, and a row decode circuit.
The memory array includes a plurality of memory cells arranged in rows and columns. The first to fourth word lines are provided correspondingly to first to fourth successively adjacent rows of the plurality of memory cells. The row decode circuit can activate one of the fist to fourth word lines according to an externally applied address signal in a normal operation, and can independently activate the first to fourth word lines from one other according to an externally applied test signal in a test operation.
According to another aspect of the present invention, a semiconductor memory device includes a memory array, bit line pairs, an equalize circuit, and a potential switch circuit.
The memory array includes a plurality of memory cells arranged in rows and columns. The bit line pairs are provided correspondingly to the columns of the plurality of memory cells and each include first and second bit lines. The equalize circuit applies an equalize potential to the first and second bit lines to equalize the potentials of the first and second bit lines. The potential switch circuit selectivity applies as the equalize potential one of a power supply potential and a ground potential to the equalize circuit a according to external setting in a test operation.
Therefore, a major advantage of the present invention is that the potentials of the four successively adjacent word lines can be controlled independently from an outside unit, and therefore various stresses due to a burn-in test can be applied and the defect elimination rate can be improved.
Another advantage of the present invention is that various stresses can be applied to memory cells and the defect elimination rate by the burn-in test can be improved further.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings